| 摘要 |
There is provided a common line number 7 signal device which exchanges signals for multi channels using one common channel. The number 7 signal device includes: a matching part(31) and a status controlling part(32) both of which are constituted in FPGA(Field Programmable Gate Array); and a rate adaption part(33) for connecting data input from a time switch block(4) to each of 32 signal link parts(200), the rate adaption part(32) being constituted in ASIC; a control part of IMP(Integrated Multiprotocol Processor) for controlling the signal link parts(200). The matching part(31) is connected to a bus matching part(22) using a bus(400) which is operated in the round robin manner.
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