| 摘要 |
PURPOSE:To decrease the circuit scale by selecting gate signals which are obtained from a fundamental clock by frequency division and differ in repetitive cycle on a time-division basis within the shortest time of each register. CONSTITUTION:This digital sound signal generating device is equipped with a processing means which processes digital sound source information, registers 141 - 144 which hold and update a processing indication signal to the processing means, a frequency dividing means 100 which divides the frequency of the fundamental clock phi to generate various gate signals, gate signal selecting means 121 and 122 which divide the minimum update time Ts of the registers by the number of pieces of digital sound source information and select various gate signals corresponding to the respective pieces of digital sound source information within the divided time, and gate means 131 - 134 which gate respective latch signals L1 - L4 supplied to the respective registers with the selected gate signals. Then processing indication signals held in the respective registers 141 - 144 are updated with the latch signals passed through the gate means 131 - 134. Consequently, the circuit scale is reduced. |
