| 摘要 |
PROBLEM TO BE SOLVED: To lock a demodulation frequency surely and economically in response to the frequency of a modulator by receiving and decoding a video and an audio signal or the like at a high bit rate. SOLUTION: An CMOS integration signal processing system includes a timing regeneration circuit to control synchronization interpolation circuits 221a, b receiving a sample at a sampling rate in which a numerical controlled oscillator 210 on chip is operated at a period T equal to an initial signal nominal baud rate. In the regeneration circuit, loop filters 259, 254, 256 are connected to the synchronization interpolation circuits and the numerical controlled oscillator and various symbol rates are processed through the configuration above. Furthermore, the system includes a carrier regeneration circuit having a digital de- rotation circuit responding to a 2nd numerical controlled oscillator and receiving an in-phase component and an orthogonal phase component of a sampled signal and an adaptive phase error estimate circuit is connected in a feedback loop. |
