Logische Schaltung mit steuerbarer Verzögerung zur Erzeugung variabler Zeitverzögerung

摘要

A controllable delay logic circuit includes a differential circuit having first and second transistors (T1, T2), a first load (RL1) coupled between a first power supply line (GND) and the collector of the first transistor, a second load (RL11) coupled between the first power supply line and the collector of the second transistor, and a constant-current source connected between a second power supply line (VEE1) and the emitters of the first and second transistors. The controllable delay logic circuit also includes a first power source (VE, VCC2), a first current path circuit (D1, RL2; T6, RL2) having a first resistor (RL2) and selectively allowing a first current to pass through the first transistor from the first power source via the first resistor, and a second current path circuit (D2, RL21; T6, RL21) having a second resistor (RL21) and selectively allowing a second current to pass through the second transistor from the first power source via the second resistor.