发明名称 |
Computer having a single bus supporting multiple bus architectures operating with different bus parameters |
摘要 |
A data processing system including a central processing unit and control circuitry on a single chip connected by a common bus to two or more bus devices having different sets of bus parameters. A first set of bus parameters functions as a memory bus for transfers to and from main memory, a second set of bus parameters functions as an I/O bus for I/O device transfers and a third set of bus parameters functions as a video bus for transfers to a video display. Each set of bus parameters has different timing selected to maximize transfers for the particular bus function (main memory, I/O, video or other) implemented by the bus parameters.
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申请公布号 |
US5630163(A) |
申请公布日期 |
1997.05.13 |
申请号 |
US19950452246 |
申请日期 |
1995.05.26 |
申请人 |
VADEM CORPORATION |
发明人 |
FUNG, HENRY T.;TSANG, SIU K.;MITCHELL, PHILLIP M.;FARQUHAR, NORMAN P. |
分类号 |
G06F13/42;G09G3/20;G09G3/36;G09G5/22;G09G5/36;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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