| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock generating device which can suppress the idling time of a CPU and reduce the power consumption of the system. SOLUTION: The clock generating device 1a is provided with a load monitor circuit 10 and a PLL type clock generator 4 which receive data TD corresponding to a task expected processing time T from a CPU 2 and the start address A1 and end address A2 of a task, and compares the actual execution time t1 of the task with the task expected processing time T to generate a UP/DOWN signal that increases the frequency of a clock signal CLK when the actual execution time t1 is longer than the expected time T or decreases the frequency of the clock signal CLK when the actual execution time t1 is shorter than the expected time T, and the PLL type clock generator 4 varies the frequency of the clock CLK according to the UP/DOWN signal and supplies the signal to the CPU 2.</p> |
