发明名称 FORMING METHOD OF VIA IN BUILD UP WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To improve wiring efficiency and reduce wiring length, by a method wherein, after a wiring layer is covered with an insulating resin layer, a viahole is formed, a plating block is grown in the viahole, and a viapad is formed. SOLUTION: An insulating resin layer 2 is formed on a resin board 10 on which a wiring pattern containing a viapad 3 is formed. A viahole reaching the viapad 3 on the surface layer of the resin board 10 is bored. The viahole is plated with electrolytic copper, and the viahole is filled with a plating block 5. The forming process of the plating block 5 is performed until the plating block 5 protrudes from the insulating resin layer 2. Then polishing is performed until the surface layer height of the plating block 5 becomes equal to the wiring pattern on the insulating resin layer 2, the viahole pad 3 is formed, and a build up layer 1' is formed. By repeating the similar processes, a plurality of build up layers 1, 1" can be formed.
申请公布号 JPH09116266(A) 申请公布日期 1997.05.02
申请号 JP19950268246 申请日期 1995.10.17
申请人 FUJITSU LTD 发明人 MAENO YOSHINOBU;KUSAYA TOSHIHIRO;IIJIMA KAZUHIKO;ISHIKAWA KOJI
分类号 H05K3/40;H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K3/40
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