| 摘要 |
PURPOSE:To reduce the number of test terminals by connecting a gate circuit between flip-flops, and inputting the result of logic arithmetic operation between a pulse whose timing is deviated by a delay circuit and the output of a flip-flop of the pre-stage to each flip-flop. CONSTITUTION:Flip-flops 11-13 and AND gates 14-16 provided to each pre- stage and delay circuits 17, 18 connected between input terminals of each of the AND gates 14-16 are components of the titled circuit. In case of the test mode, the clock input 102 goes to '1' and two consecutive clock pulses are supplied the test input 103 to input two pulses whose timing is deviated to all the flip-flops 11-13 and the result is observed by the output of the final flip-flop. Thus, the test time is reduced and it is not required to extend the terminal for the test output. |
