发明名称
摘要 PURPOSE:To perform data transfer at high speed without increasing the number of signal lines, by setting a mode at a DMA mode by analyzing a reception data, and performing DMA transfer until the completion processing of a telegram is performed by an interruption signal. CONSTITUTION:A multi-parallel data received at a reception data signal line 11 and a strobe signal line 12 is fetched in a reception response circuit 1, and the busy of a reception processing is transmitted to a transmitter via a busy signal line 13. The reception data is stored in a reception buffer 3, and a microprocessor 2 analyzes the reception data, and when the data is a bit of DMA start information, the processor executes a DMA transfer instruction on the circuit 1, and sets the mode at a DMA transfer mode. When the reception data is transferred from the circuit 1 to the buffer 3, and also, a time monitoring time 4 arrives at a set time, the transfer is completed and the completion processing of the telegram by sending it to the interruption signal line 20. In such a way, it is possible to perform the data transfer at high speed without increasing the number of the signal lines.
申请公布号 JP2605273(B2) 申请公布日期 1997.04.30
申请号 JP19870039216 申请日期 1987.02.24
申请人 发明人
分类号 G06F13/28;(IPC1-7):G06F13/28 主分类号 G06F13/28
代理机构 代理人
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