DRAM having test circuit capable of performing function test of refresh counter and measurement of refresh cycle simultaneously

摘要

According to the present invention, there is provided a circuit structure capable of carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation. The counter generates a refresh row address. The bit line sense amplifier circuit connected to a bit line pair for transmitting data of a memory cell, consists of the N-channel sense amplifier and the P-channel sense amplifier. The sense amplifier driving circuit supplies respective driving signals for the N-channel sense amplifier and the P-channel sense amplifier. The test control circuit is provided for carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation, and controls the driving signals so as to set one of the N-channel sense amplifier and the P-channel sense amplifier in a non-active state at the time of a test mode.