| 摘要 |
A power usage simulator generates, for all the logic cells in a circuit cell library, a power model that characterizes a cell's power consumption behavior as a two-part, piecewise-linear function based on signal slew rates and output load. A logic simulator is modified so that for each signal transition in a specified logic circuit, the logic simulator performs a power usage computation utilizing the power usage model for all cells affected by each signal transition. The power usage value for each signal transition is posted to a power usage output data structure, with each posted power usage value having an associated time value. The posted power usage values are then analyzed by (A) accumulating the posted power usage values to provide a total power usage value, and (B) clocking the accumulation of power usage values with an end user set clock rate so as to produce a power usage profile indicating the time varying rate of power consumption during the simulation time period. The clocked accumulation of power usage enables easy detection of whether the peak rate of power consumption during the simulation time exceeds a specified threshold (e.g., a threshold associated with a particular power bus design). Thus, data generated by the power usage simulation may be used, either directly or indirectly to determine that the simulated logic circuit requires a larger power bus design, or that the logic circuit should be modified so as to reduce its peak power usage rate.
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