| 摘要 |
A parallel processing apparatus of a superscalar type includes an instruction decoding stage which decodes four instructions simultaneously fetched from an instruction memory and issues instructions which allows simultaneous execution to related function units. The instruction decoding stage includes an instruction decoder which decodes the instruction and issues the instructions allowing simultaneous execution to the function units, and a queue which queues and stores the instructions fetched from the instruction memory. This instruction decoding stage also includes a scope logic which forms a read queue address for reading the instructions of the queue in accordance with the number of issued instructions in the instruction decoder and whether a branch is generated by a branch instruction, and a queue top logic which forms a write address in the queue in accordance with a storage state of an unissued available instruction in the queue. Instructions are read from four successive addresses starting from the read address. Fetched instructions are stored in four addresses in the queue starting from the write address. Four instructions to be decoded are always supplied to the instruction decoder in accordance with an issue state of the instructions. Four instructions are always fetched from the instruction memory and queued. Therefore, the instructions can be efficiently supplied to the instruction decoder in accordance with the execution state of the instructions.
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