THE MULTIPLEXER OF A HIGH SPEED BIT DATA

摘要

A multiplexer uses a bite clock being input to a retiming circuit(11) and the parallel road pulse generator(12), uses a bit clock being input to the parallel road pulse generator(12) and the parallel/serial converter(13), makes a dependent relation between jitters of the bite clock and the bit clock, stably maintains a retiming input parallel data, generates an output serial data from a rising transition next to a rising transition of the bit clock generating the load pulse, and provides an accurate multiplexer about a high-speed bit data. The high-speed bit data multiplexer includes: a bit synchronizing part(30) for retiming a bite clock by using a rising transition of the bit clock, and providing a retiming bite clock and bit clock; a retiming part(34) for retiming a plurality of input parallel data by using a rising transition of the retiming bite clock, aqnd outputting a retiming parallel data; a parallel load pulse generator(35) for generating a load pulse providing a serial conversion point of the retiming parallel data; and a parallel/serial convertor(36) for converting the parallel data to a serial data from a rising transition point next to a rising transition of the bit clock.