发明名称 AN ASYMMETRIC SWITCH ARCHITECTURE FOR USE IN A NETWORK SWITCH NODE
摘要 <p>In a network switch node, an asymmetric switch. The asymmetric switch comprises a plurality N of inputs each for coupling to a corresponding one of a plurality N of port modules and a plurality M of outputs each for coupling to one of the plurality of port modules. M is greater than N such that at least one of the plurality of port modules is coupled to more outputs than inputs. The asymmetric switch also includes a switching fabric operative to switch packets received from the inputs to the outputs. According to one embodiment, M = kN such that each port module can have one input line to the asymmetric switch and k output lines from the asymmetric switch. Such an asymmetric switch-to-port interface results in less blocking and allows output buffering wherein the output buffers are provided at the ports, rather than at the switch.</p>
申请公布号 WO1997012494(A1) 申请公布日期 1997.04.03
申请号 US1996014637 申请日期 1996.09.12
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