| 摘要 |
A controller commands the memory refreshment of a pseudo-static random access memory (PSRAM) accessible from a remote host processor. The controller includes a detector for the end of a memory access cycle by the host processor. A tapped delay line is activated by the detector at the end of the memory access cycle of the PSRAM. The tapped delay line produces a series of delay line output signals at a series of preselected times after activation. An automatic refresh of the PSRAM is initiated upon receipt of a first tapped delay line output signal. The automatic refresh is discontinued upon receipt of a second tapped delay line output signal that follows the first tapped delay line output signal by a sufficient time to permit performance of an automatic refresh. Further refresh cycles can be initiated if the host does not seek memory access, and the further refresh cycles can begin immediately or be delayed by some selected amount of time.
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