| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a timer circuit which can suppress the increase of the circuit area while securing the bit length. SOLUTION: A counter 2 counts the count clock signals CLK to output the count data D0 to Dm of plural bit length. A register 3 stores the data R0 to Rm of bit length smaller than the bit length of the counter 2. A control circuit part 5 changes one of data R0 to Rn stored in the register 3 when the data D0 to Dm are inputted and then reach the count limit value. A time-up signal generation circuit 10 outputs a time-up signal INT when the data R0 to Rn stored in the register 3 and the data D0 to Dm reach the limit value respectively.</p> |
