发明名称 |
VIDEO SIGNAL MAGNIFYING AND REDUCING DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To realize magnifying/reducing processing at an optional magnification by the signal processing of a single clock. SOLUTION: A memory circuit 2 temporarily stores an input video signal from an input terminal 1. A writing control circuit 16 inhibits the memory circuit 2 from writing corresponding to the horizontal compressibility of a video to thin the picture element of the input video signal. A reading control circuit 17 inhibits the memory circuit 2 from supplying a read clock corresponding to the horizontal magnification of the video and controls it to repeatedly read the picture element of the input video signal. An interpolation filter circuit 3 gives filtering processing by means of an interpolation coefficient corresponding to the horizontal scaling factor of the video to the output signal of the memory circuit 2 to attain a smooth and horizontally magnified/compressed video. A scaling factor control circuit 15 controls the interpolation coefficientβat the writing control circuit 16 and the interpolation filter 3 corresponding to the compressibility at the time of horizontally compressing the video, and controls the interpolation coefficientβat the reading control circuit 17 and the interpolation filter 3 corresponding to the magnification at the time of horizontally magnifying the video.
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申请公布号 |
JPH0983960(A) |
申请公布日期 |
1997.03.28 |
申请号 |
JP19950241961 |
申请日期 |
1995.09.20 |
申请人 |
HITACHI LTD;HITACHI VIDEO IND INF SYST INC |
发明人 |
ISHIBASHI KOICHI;KURITA TOSHIYUKI;TAKADA HARUKI |
分类号 |
H04N5/91;H04N3/223;H04N7/01;(IPC1-7):H04N7/01 |
主分类号 |
H04N5/91 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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