Method for increasing system bandwidth through an on-chip address lock register

摘要

A computer system comprising one or more processor modules. Each processor module comprising a central processing unit comprising a storage element disposed in the central processing unit dedicated for storing a semaphore address lock value and a semaphore lock flag value, a cache memory system for storing data and instruction values used by the central processing unit, a system bus interface for communicating with other processor modules over a system bus, a memory system implemented as a common system resource available to the processor modules for storing data and instructions, an IO system implemented as a common system resource available to the plurality of processor modules for each to communicate with data input devices and data output devices, and a system bus connecting the processor module to the memory system and to the IO system.