| 摘要 |
At the time of erasing, the erase verification is not effected but the erase voltage is repetitively applied to the source of a memory cell until it is so judged that the erase current IA flowing into the source of the memory is smaller than the reference current IB and when it is judged that the erase current IA flowing into the source of the memory cell is smaller than the reference current IB, application of the erase pulse to the source of the memory cell and the erase verification are repetitively effected. As a result, in the flash memory device, it is possible to decrease the number of times of erase verification and reduce the time required for the erasing.
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