发明名称 |
Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines |
摘要 |
A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.
|
申请公布号 |
US5615156(A) |
申请公布日期 |
1997.03.25 |
申请号 |
US19940250130 |
申请日期 |
1994.05.27 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED;HITACHI, LTD. |
发明人 |
YOSHIDA, HIROYUKI;INUI, TAKASHI;NUMAGA, SHIGEKI;NAKAI, KIYOSHI;SUZUKI, YUKIHIDE |
分类号 |
G11C11/401;G11C29/00;G11C29/04;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):G11C29/00 |
主分类号 |
G11C11/401 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|