| 摘要 |
A circuit for generating bit line precharge voltage of semiconductor device is disclosed. A DRAM includes NMOS type cell transistor. The circuit comprises a semi voltage output portion transferring a half voltage(vcc/2) to an output terminal(vblp), a substrate voltage transfer portion transferring a substrate voltage to the output terminal, a half voltage output portion transferring the substrate voltage to the output terminal for a constant time after a supply voltage is applied to the DRAM and after a certain time has passed, while transferring the half voltage to the output terminal, and a to the pulse signal generation portion outputting a pulse signal to control the substrate voltage transfer portion. Thus, over-current, noise, and latch-up can be reduced.
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