发明名称 |
ERROR DETECTION A ND CORRECTION SYSTEM FOR MEMORY UNIT |
摘要 |
PURPOSE:To reduce the quantity of the hardware and to increase the reliability, by making sufficient for the correction circuit with only one circuit, thru the performance of only detection for the data transfer from the memory unit of low speed and large capacity to CPU, and thru the performance of equivalent error correction by retransmitting the data to CPU even with error. |
申请公布号 |
JPS5324736(A) |
申请公布日期 |
1978.03.07 |
申请号 |
JP19760099265 |
申请日期 |
1976.08.20 |
申请人 |
NIPPON TELEGRAPH & TELEPHONE |
发明人 |
FUKUDA HARUYUKI;ISHIKAWA TSUTOMU;KOSUGE YASUHARU |
分类号 |
G06F11/10;G06F11/00;G06F12/08;G06F12/16;G11C29/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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