| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a constant and high-speed operation by shortening gate lengths of transistors of latch circuits while commonly providing sense-amplifiers to plural bit lines and while providing latch circuits apart from these sense- amplifiers. SOLUTION: Information are read out from memory cells M1-M116 and are amplified by selecting switches SS111-224 connected to bit lines D11-28 of a word line W1 and by connecting them to sense-amplifiers S11-22 commonly provided to them. When sufficient signals are obtained at sense-amplifiers, signals are transferred to IO1, 2 lines by successively changing over selection switches Y11-22. In the case of a writing, information are written in sense- amplifiers S11-22 from IO1, 2 lines and the information are transferred to latch circuits L111-224 via switches SL111-224, SL111-224 and also are written in memory cells M11-116. In this case, MOS transistors having short gate lengths are used in latch circuits. Thus, the chip area is downsized and the high-speed and constant operation is obtained.</p> |
