Data processor with operation units executing dyadic and monadic operations sharing groups of register files with one of the units exclusively accessing one of the register files

摘要

A data processor of modular architecture comprises a plurality of operation units, each serving to implement specific functionalities as required by the instruction set that determines the processor's operation. Register files for several ones among the operation units are merged. At least one of the register files is exclusively assigned to one of the operation units. At the expense of only a marginal increase, if any, of the number of instruction cycles, smaller register file areas in an IC embodiment, less register file control circuitry and simpler microcode words are obtained.