发明名称 |
Multibus cached memory system |
摘要 |
<p>A method and apparatus for implementing a multibus cache memory system for use in computer systems is disclosed utilizing a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles. <IMAGE></p> |
申请公布号 |
EP0762287(A1) |
申请公布日期 |
1997.03.12 |
申请号 |
EP19960304565 |
申请日期 |
1996.06.19 |
申请人 |
RAMTRON INTERNATIONAL CORPORATION |
发明人 |
JOSEPH, JAMES DEAN;HEISLER, DOYLE JAMES;HEISLER, DION NIKOLAS |
分类号 |
G06F12/08;G06F13/18;G06F13/40;(IPC1-7):G06F12/08;G06F13/16 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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