Digital frequency demodulator

摘要

The demodulator includes a counter (C1), with a validation input receiving a logical signal (Fe) derived from a frequency modulated analog signal (Se). A clock signal (H) is applied to a second input (C1). The clock frequency is higher than the logical signal frequency so that it can be considered time independent. The counter measures the number of pulses (p) in the clock signal during a period (Te) of the logical signal Fe. The measurement is repeated for a number of cycles. at the end of these cycles the information is transmitted to a buffer register.