发明名称
摘要 <p>PURPOSE:To execute a picture processing at high speed by transferring the intermediate result of the picture processing of a local picture processor to the other processor. CONSTITUTION:A picture signal and one horizontal line delayed and two horizontal line delayed picture data are inputted to a local picture register 1 to store a local picture. A clock control circuit 5 controls the picture fetching of the local picture register 1, the arithmetic output of an arithmetic block 12 and a program control circuit 4. A transfer register 13 is a FIFO register, it inserts the intermediate result of a calculation in the arithmetic block 12, and transfered to the external processor. In addition, a receiving register 14 stores the intermediate result of the calculation of the external processor as an input.</p>
申请公布号 JP2589781(B2) 申请公布日期 1997.03.12
申请号 JP19880198207 申请日期 1988.08.09
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MARUYAMA MASAKATSU
分类号 G06F15/16;G06T1/20;G06T5/20;(IPC1-7):G06F15/16 主分类号 G06F15/16
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