发明名称 TIME COUNTER CIRCUIT, SAMPLING CIRCUIT, LOGIC DISCRIMINATION CIRCUIT AND SKEW ADJUSTMENT CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To realize the time count circuit measuring a pulse interval of pulse signals with high accuracy immune to fluctuation in a power supply voltage. SOLUTION: A delay circuit ring 11 is configured by connecting plural delay circuits in a ring and signal transition is circulated. A switch signal generating circuit 12 provides an output of 1st switch signal 12a and a 2nd switch signal 12b based on a timing of a leading of a pulse signal being a measurement object. A sampling circuit array 13 is made up of plural sampling circuits connecting to each output terminal of each delay circuit and a signal at the output terminal of the delay circuit is sampled according to a command of a 1st switch signal 12a. A hold circuit array 14 is made up of plural hold circuits connecting to the output terminal of each sampling circuit to hold the signal at the output terminal of the sampling circuit according to a command of the 2nd switch signal l2b. An arithmetic circuit 15 converts a logic level signal outputted from the hold circuit array 14 into time data.</p>
申请公布号 JPH0964742(A) 申请公布日期 1997.03.07
申请号 JP19960144368 申请日期 1996.06.06
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KUSUMOTO KEIICHI;MATSUZAWA AKIRA
分类号 G04F10/04;G01R19/165;G01R29/02;G06F1/10;G11C27/02;H03K23/00;H03M1/50;(IPC1-7):H03M1/50 主分类号 G04F10/04
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