| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide the arithmetic synchronizing circuit which can suppress a decrease in operation speed and prevent malfunction of arithmetic operation due to signal delay of a clock signal. SOLUTION: This circuit is equipped with an input synchronizing circuit group 11 which inputs the most significant-least significant digits of input data A and B in synchronism with a clock signal CK2 and outputs synchronized data Aa and Ba, an arithmetic circuit 12 which receives and processes the outputs of the input synchronizing circuit group and generates a sum output and a carry output, a 1st adding circuit group 13 which adds the sum output of low-order P digits of the arithmetic circuit and data of corresponding digits of the carry output together, an output synchronizing circuit group 14 which inputs the sum output of high-order digits of the arithmetic circuit, the most significant-least significant digits of the carry output, the sum output of the 1st adding circuit group in synchronism with a clock signal CK1, and the most significant-least significant digits of the carry output, and a 2nd adding circuit group 15 which adds the sum output of high-order digits of the output synchronizing circuit group, the carry output, and the carry output of low-order digits.</p> |
