Single-chip processor with external test function

摘要

An instruction memory (1) holds command codes, an addressing device (2), a data input device (6) for entering test command codes, a decoder (7) and a selection device (9,10,11) inserted between the command memory, the data input device and the decoder. In the normal operating mode of the selection device, the instruction codes from the instruction memory are fed to the decoder and in a test mode the test instruction codes from the data input device are fed to the decoder.