| 摘要 |
The apparatus includes a column address buffer memory (1), two column decoders (2,2') connected to the buffer memory, two read amplifiers (3,3'), and a data amplifier. Two first stages (4,4') of the data amplifier are respectively connected to two read busses (RIO1,RIO2). A data intermediate circuit (7) is connected to the second stage of the data amplifier (6). Provided with the address buffer is a burst counter and two address signals (YADD1,YADD2) are produced synchronously with every second clock signals. The two decoders receive respective buffer signals synchronously with each second clock signal. Data signals compatible with respective column switch signals (YSW1,YSW2) of the respective column decoders are received by the read amplifiers and applied to the read busses. The read amplifier stages amplify voltages on the read busses and transfer them to a read/write bus (RWBS1) at every second clock signal, the stages being multiplexed so that signals from each first stage are alternately applied to the amplifier second stage (6) via the read/write bus. The intermediate circuit outputs data from the amplifier second stage with every single clock pulse.
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