| 发明名称 |
Planarized final passivation for semiconductor devices |
| 摘要 |
<p>A final passivation structure for a semiconductor device having conductive lines (102) formed on a surface of the semiconductor device, comprising a planarized layer (104) covering the surface and also covering the conductive lines (102), and a diffusion barrier (108) covering the planarized layer (104). Alternately, the planarized layer (104) may partially cover the conductive lines (102). <IMAGE></p> |
| 申请公布号 |
EP0759635(A2) |
申请公布日期 |
1997.02.26 |
| 申请号 |
EP19960305672 |
申请日期 |
1996.08.01 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;SIEMENS AKTIENGESELLSCHAFT;KABUSHIKI KAISHA TOSHIBA |
发明人 |
RYAN, JAMES GARDNER;MITWALSKY, ALEXANDER;OKUMURA, KATSUYA |
| 分类号 |
H01L21/31;H01L21/316;H01L21/768;H01L23/31;H01L23/522;H01L23/532;(IPC1-7):H01L23/31 |
主分类号 |
H01L21/31 |
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