发明名称 |
Dynamic clocked inverter latch with reduced charge leakage |
摘要 |
A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith. During inactive states of the clock signal, the first N-MOSFET becomes reverse-biased by the output node discharge voltage, while during inactive states of the inverse clock signal, the second P-MOSFET becomes reverse-biased by the output node charge voltage, thereby virtually eliminating charge leakage to and from the output node, respectively.
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申请公布号 |
US5606270(A) |
申请公布日期 |
1997.02.25 |
申请号 |
US19940357607 |
申请日期 |
1994.12.16 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
D'SOUZA, GODFREY P.;TESTA, JAMES F.;LAIRD, DOUGLAS A.;BURR, JAMES B. |
分类号 |
H03K3/356;H03K19/00;H03K19/096;(IPC1-7):H03K19/20 |
主分类号 |
H03K3/356 |
代理机构 |
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