发明名称 SPEED CONTROLLER FOR DC MOTOR
摘要 PROBLEM TO BE SOLVED: To perform PLL correction automatically even if the load fluctuates during operation without requiring any time for manually regulating the PLL by regulating the D/A set data for altering the duty of PLL pulse thereby shifting the PLL control range. SOLUTION: In the automatic PLL regulation process, a D/A set data for altering the duty of PLL pulse is adjusted depending on the frequency difference and phase difference delivered from a PLL control section 30 thus shifting the PLL control range. In the rough regulation process, the r.p.m. of a DC motor is detected based on the FB+, FB- pulses corresponding to frequency signal and the D/A set data is adjusted such that the r.p.m. comes within the PLL control range. In a fine adjusting process, the D/A set data is adjusted such that the control can be carried out in the center of PLL control based on the phase difference between a speed clock MMTCLK corresponding to a reference signal and the FB+, FB- pulses corresponding to frequency signal.
申请公布号 JPH0947063(A) 申请公布日期 1997.02.14
申请号 JP19950190489 申请日期 1995.07.26
申请人 KONICA CORP 发明人 ANZAI EIJI;SUGANO MASASHI;ARAI HIROYUKI
分类号 G03G21/00;H02P7/29 主分类号 G03G21/00
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