| 摘要 |
<p>Disclosed is a sense amplifier circuit of nonvolatile semiconductor memory device with NAND structured cells, comprising a bit line isolation section (12) located between a pair of bit lines (BLi,BLj) connected to a memory cell array (100) and a pair of sub-bit lines (SBLi,SBLj) connected to an input/output gate circuit (200), a latch type voltage controlled current source (13) having n-channel MOS transistors (Q21,Q22) connected to the sub-bit lines (SBLi,SBLj), and a switching section (14) connected between the voltage-controlled current source (13) and a signal line (VSA), wherein the bit lines (BLi,BLj) are electrically and completely isolated from the sub-bit lines (SBLi,SBLj) by means of the bit line isolation section (12) receiving an isolation control signal (ISA) during the sensing operation. With the circuit, the sensing operation is not affected by a bit line load impedance, and thereby the sensing speed is improved in addition to the reduction of a peak current along the data path therein. <IMAGE></p> |
