发明名称 HIGHLY RELIABLE COMPUTER SYSTEM
摘要 PROBLEM TO BE SOLVED: To prevent a fault of an IO side from being affected on the inside of a CPU and to continue the processing by using a substitute IO. SOLUTION: CPUs 1A, 1B execute the same processing usually synchronously with the same clock. Various input output devices or the like are connected to input output bus adaptors (IOBA) 20A, 20B via input output buses 30A, 30B. The CPUs 1A, 1B and the IOBAs 20A, 20B are connected via a connector 2. The connector 2 is made up of a duplicate system bus adaptor(DSBA) consisting of DSBAp-A, DSBAs-B, and DSBAp-B, DSBAs-A, in pairs. The connector 2 monitors access of the CPUs 1A, 1B and the IOBAs 20A, 20B and disconnects a faulty CPU on the occurrence of a fault in the CPU and disconnects a faulty input output bus by the instruction of the CPUs 1A, 1B on the occurrence of a fault at the IO.
申请公布号 JPH0934809(A) 申请公布日期 1997.02.07
申请号 JP19950181222 申请日期 1995.07.18
申请人 HITACHI LTD 发明人 OGURO HIROSHI;YAMAGUCHI SHINICHIRO;MIYAZAKI YOSHIHIRO;TAKATANI SOICHI;HIRAMATSU MASATAKA;AKEURA NOBUO
分类号 G06F11/00;G06F11/16;G06F11/20;G06F11/30;G06F13/00;G06F15/16 主分类号 G06F11/00
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