| 摘要 |
PROBLEM TO BE SOLVED: To decrease the number of test terminals and the number of times of test for memory cell array by providing means for connecting one bit line of a memory cell with one bit line of an adjacent memory cell at the time of test. SOLUTION: When an 'H' level normal/test mode signal is applied from an RAM to a test input circuit 21, a bit line connection circuit C1-C31 connects one bit line of m×n matrix memory cell(MC) in a memory cell array 15, e.g. a static RAM, with one bit line of an adjacent MC through a transfer gate. The word line is selected sequentially for each row by inputting a test signal to the bit line of first row and read out from the bit line of m-th row through a terminal T3. Consequently, the MC of m×n matrix can be tested in serial for each word line while decreasing the number of times of test.
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