| 摘要 |
PROBLEM TO BE SOLVED: To reduce the power consumption of the circuit by stopping power supply to a master PLL while a sampling value is being held. SOLUTION: When a reference signal Sref is given to a master PLL 1, the PLL1 synchronously therewith allows a 1st VCO 5 to provide the signal Sref and a frequency signal. In this case, a 1st loop filter 4 provides an output of a stable DC voltage to the VCO 5 and a sample-and-hold circuit 7. When a data signal SD is given to a slave PLL 2 in the synchronization state of the PLL 1, a 2nd VCO 1 provides an output of a signal SD synchronously with the timing signal SD in the signal SD. When a timer signal ST is at a high level, the circuit 7 samples an output of the filter 4 and provides an output of the sampled signal to a signal adder circuit 10. On the other hand, when the signal ST is at a low level, the circuit 7 keeps an output of the filter 4 just before the signal ST changes from a high level to a low level and it is outputted to the circuit 10. Since the power supply is stopped from a power supply circuit 6, the power consumption of the PLL 1 is reduced. |
