发明名称 ON-CHIP VACUUM PACKAGE TECHNOLOGY FOR MICROMECHANICAL DEVICES
摘要 A process for manufacturing a vacuum enclosure for a semiconductor device formed on a substrate with leads extending peripherally, and the product manufactured by the process. In a first embodiment, an intrinsic silicon shell (10) is sealed to the substrate (12) via electrostatic or anodic bonding with the leads (16) diffusing into the shell. In a second embodiment, a thin interface layer (18') of silicon or polysilicon is deposited on the substrate (12') prior to electrostatic bonding a glass shell (10') thereon. In a third embodiment, tunnels (30'') are formed between a lower peripheral edge of the shell (10'') and the substrate (12''), allowing leads (16'') to pass thereunder. The tunnels are sealed by a dielectric material (14'') applied over the enclosure.
申请公布号 WO9703459(A1) 申请公布日期 1997.01.30
申请号 WO1996US11415 申请日期 1996.07.08
申请人 THE CHARLES STARK DRAPER LABORATORY, INC. 发明人 CHO, STEVE, T.
分类号 G01P1/02;H01L21/50;H01L23/057;(IPC1-7):H01L21/52;H01L21/54;H01L21/56;H01L21/60;H01L23/08;H01L23/15;H01L23/29;H01L23/31;H01L23/535 主分类号 G01P1/02
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