发明名称 Semiconductor memory system
摘要 A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input/output circuit corresponding to a defective chip address; a data input/output portion for selectively activating an input/output circuit to be connected to a data bus corresponding to a dynamic RAM found defective; and a mask portion for outputting a control signal for putting in a high-impedance state an output pin of the defective RAM in a read operation.
申请公布号 US5598373(A) 申请公布日期 1997.01.28
申请号 US19950476765 申请日期 1995.06.07
申请人 HITACHI, LTD.;HITACHI ULSI ENGINEERING CORP. 发明人 WADA, SHOJI;KENMIZAKI, KANEHIDE;MURANAKA, MASAYA;OGATA, MASAHIRO;AOYAGI, HIDETOMO;KITAME, TETSUYA;KATAYAMA, MASAHIRO;KUBONO, SHOJI;SUZUKI, YUKIHIDE;MORINO, MAKOTO;MIYATAKE, SINICHI;SHUNDO, SEIICHI;KOYAMA, YOSHIHISA;OHNO, NOBUHIKO
分类号 G06F12/16;G11C29/00;G11C29/02;G11C29/44;H01L21/82;(IPC1-7):G11C7/00;G11C8/00;G11C11/34 主分类号 G06F12/16
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