发明名称 CLOCK GENERATOR
摘要 PROBLEM TO BE SOLVED: To reduce the variation of dead time generated by the change in temperature or.power supply voltage. SOLUTION: A clock generator 1 is constituted of a time constant circuit 2 and two threshold circuits 3, 4 arranged in parallel with the output of the circuit 2 and having respectively different threshold voltage values. The 1st threshold circuit 3 for obtaining a 1st phase clock signal ϕ1 to be a non-inverted output by judging the output of the circuit 2 by a 1st threshold VTH1 is constituted of the combination of inverters 3a, 3b having the circuit threshold VTH1 . The 1st threshold VTH1 is set up to a value higher than 1/2 VDD e.g. The 2nd threshold circuit 4 obtains a 2nd phase signal ϕ2 to be an inverted output by judging the output of the circuit 2 by a 2nd threshold VTH2 . The threshold VTH2 is set up to a value lower than 1/2 VDD.
申请公布号 JPH0923144(A) 申请公布日期 1997.01.21
申请号 JP19950196993 申请日期 1995.07.10
申请人 YAMAHA CORP 发明人 SUZUKI TOSHIHIKO
分类号 H03K5/151 主分类号 H03K5/151
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