| 摘要 |
PURPOSE: To reduce a time required for a synchronous addition processing to half by sampling reference signal by a frequency of an integral multiple of a reference rate by a synchronous addition processor for eliminating the noise of the reference signal and performing a synchronous addition processing to all read data. CONSTITUTION: The 32.4MHz rate data of a VITS#1 at the time of CSS=0 hour are fetched for N/4 times and the 32.4MHz data of the VITS#1 at the time of CSS=1 hour are fetched for N/4 times in a VITS#1 synchronous addition part 12. In this case, when the data of CSS=1 hour are shifted by one sampling by 32.4MHz and a phase is matched, N/2 pieces of the VITS#1 waveforms of a 32.4MHz rate are obtained and an addition processing is performed for N/2 times. Since the output of the synchronous addition of the VITS#1 is added and averaged with a VITS#2, polarity is inversed by a polarity inversion part 11. Similarly, in an addition part 13, the total of N/2 pieces of the VITS#2 waveforms of the 32.4MHz rate are obtained. The averaging processing of the addition part 13 and the output of the polarity inversion part 11 is performed in an averaging processing part 10. The output of a synchronous addition processing part 9 becomes the synchronous addition data for N times of the 32.4MHz rate data of the VITS. |
