发明名称 PARALLEL/SERIAL CONVERSION CIRCUIT
摘要 PURPOSE: To make a high speed operation possible by operating a flip-flop for serial data output just before the selector of the final stage in synchronization with the output period of serial data and to suppress power consumption by reducing a circuit part operating at high speed. CONSTITUTION: The outputs of flip-flops 31 and 33 are inputted in a selector 36 and the outputs of flip-flops 32 and 34 are inputted in a selector 37, so that the outputs of bits which become adjacent with each other may not be inputted in the same selector when data becomes serial data. Further, the both of the outputs of the selectors 36 and 37 are inputted in the selector 38 of the next stage (final stage). The output of the selector 38 of the final stage is inputted in the flip-flop 35 just before. This flip-flop 35 becomes a flip-flop for serial data output. The flip-flop 35 is operated by the clock CLK01 operating in synchronization with the period of serial data.
申请公布号 JPH096591(A) 申请公布日期 1997.01.10
申请号 JP19950147405 申请日期 1995.06.14
申请人 HITACHI LTD 发明人 WATABE YOSHIHISA
分类号 G11C19/00;G06F5/00 主分类号 G11C19/00
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