| 摘要 |
<p>An FPGA including SRAM memory cells (400), each having a latch configured so that both read and write signals are provided through the data path connection. By providing both read and write through the data path, the FPGA further includes only a single decoder to control pass gates connected to the memory cells (400) during read and write. To prevent voltages during write from damaging pass gates in the data path, the FPGA further includes a modified power supply to provide voltages ranging from VDD to VSS to the memory cell transistors (414, 416, 418, 420) during read, while providing a reduced voltage range during write to enable memory cell states to more easily be altered.</p> |
