发明名称 Process for manufacturing a high-voltage withstanding planar p-n junction
摘要 <p>Starting from a planar pn junction (12a, 12b) which isolates a semiconductor region (11a, 11b) of a first conduction type from a semiconductor body (1) of a second conduction type, the peripheral region (11b) of the semiconductor region having a lateral doping gradient over its entire width, which exceeds the penetration depth of the semiconductor region, a part of the peripheral region (11b) is removed in an etching step. The etching depth (17) is so dimensioned that the surface breakdown voltage of the p-n junction (12a, 12b) is adjusted to specified value. <IMAGE></p>
申请公布号 EP0389863(B1) 申请公布日期 1996.12.18
申请号 EP19900104737 申请日期 1990.03.13
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 SCHULZE, HANS-JOACHIM, DR.;KUHNERT, REINHOLD, DR.
分类号 H01L29/73;H01L21/033;H01L21/22;H01L21/225;H01L21/265;H01L21/329;H01L21/331;H01L21/332;H01L29/06;H01L29/36;H01L29/74;(IPC1-7):H01L21/225 主分类号 H01L29/73
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