| 摘要 |
PURPOSE: To obtain a demodulator circuit including a circuit for extracting a clock from an input data in which the demodulator circuit is controlled not to produce an abnormal demodulation data until the input data is synchronized with an extracted clock. CONSTITUTION: A clock 11 is extracted from a digital audio interface input RX and a circuit 13 detects synchronism with the RX to produce a synchronism detection signal DILOCK. A C bit data demodulated from the RX through a demodulation circuit 14 is delivered to an output circuit 15. The output circuit 15 adds a control flag, indicating the state synchronized with the DILOCK, to the head of an output data. The control flag is set to '0' during the interval before detection of synchronism (DILOCK=L) and set to '1' upon detection of synchronism (DILOCK=H) thus representing the validity of C bit data being synchronized. |
