Systempro emulation in a symmetric multiprocessing computer system

摘要

Computer systems which emulate the operation of the Systempro and the Systempro registers, even though they are symmetric multiprocessors developed using the Intel P54C and P54CM or their equivalents. Further, the APICs in the systems are configured to emulate the interrupt handling of the Systempro. The FLUSH and CACHEON bits are emulated by flushing both processors and an external cache upon setting of the FLUSH bit or toggling of the CACHEON bit if the processors are the P54C and P54CM in a dual processor configuration. If the processors include separate level 2 caches, the CACHEON bit controls the enablement of the caches and the FLUSH bit causes a flushing of the caches for the respective processor. The SLEEP bit for the second processor is emulated by providing an initialization IPI to the second processor APIC without providing a startup IPI, and the RESET register bit is ignored.