发明名称 Retiming arrangement for sdh data transmission system
摘要 A retiming arrangement for use in a demultiplexer in an SDH data transmission system uses Bit Justification data, and not Pointer data, to modify a recovered clock signal and generate a clock signal for retiming purposes. The invention is especially for use in enabling third party users to carry primary rate timing data across an SDH network.
申请公布号 AU5509696(A) 申请公布日期 1996.11.21
申请号 AU19960055096 申请日期 1996.05.03
申请人 GPT LIMITED 发明人 IAIN JAMES SLATER
分类号 H04J3/00;H04J3/06;H04J3/07 主分类号 H04J3/00
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