| 摘要 |
A process for fabricating memory cells for split-gate flash memory devices is disclosed to feature self-alignment and therefore precisely defined channel lengths for the floating-gate and isolation transistors of the memory cell. A gate oxide layer, a first conducting layer, and a gate dielectric layer are formed in sequence on a semiconductor substrate. A conducting strip is formed on the gate dielectric layer. The conducting strip is covered with a shielding layer. The gate dielectric layer, the first conducting layer and the gate oxide layer are etched utilizing the shielding layer as a shielding mask to form a control gate for the memory cell. Thermal oxidation is applied to the entire substrate utilizing the shielding layer as a shielding mask to form a tunnel oxide layer on the surface of the substrate and isolating oxide layers on the sidewalls of the control gate. The shielding layer is removed. Electrically conducting sidewall spacers are formed on both of the sidewalls of the conducting strip. Each of the conducting sidewall spacers cover a portion of the tunnel oxide layer and are also electrically isolated from the control gate by the isolating oxide layer, forming the floating gate for the memory cell. Impurities are implanted utilizing the conducting strip and the conducting sidewall spacers as shielding masks to form source and drain regions on the substrate for the memory cell.
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