| 摘要 |
PURPOSE: To correctly make a parity check even in a device wherein data order is inverted between its input side and output side by changing the order of parity signals generated on the input side by the same method as data signals and outputting them, and comparing the parity signals and data signals. CONSTITUTION: A signal selection part 3 rearranges (n) data inputted from a series-parallel conversion part 1 according to frame synchronous pattern head bit detection information. Input-side parity generation parts 41 -4n generate (n) parity signals which are considered as outputs of a signal selection part from (n) input data of the signal selection part 3. A parity selection part 6 selects the outputs of the input-side parity generation parts 41 -4n with the same logic with the signal selection part 3. And, an output-side parity generation part 5 generates parity bits at a time from all the bits on the same time slot of the respective signals with (n) output signals of the signal selection part 3 and a parity check part 7 compares them with the parity bits selected by the parity selection part 6. |
